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Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
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Low-Dose CT Image Denoising Using a Generative Adversarial Network With Wasserstein Distance and Perceptual Loss
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Low-Dose X-ray CT Reconstruction via Dictionary Learning
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Low-PAPR Spatial Modulation for SC-FDMA
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Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
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Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop
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Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
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Low-Power Dual Dynamic Node Pulsed HybridFlip-Flop Featuring Efficient Embedded Logic
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Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
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Low-Power Programmable PRPG With Test Compression Capabilities
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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through
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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
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