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Home / programming language / Online Matlab Projects / Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through
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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

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SKU: PROJ2087 Categories: 2013 Projects, 2015 Projects, Final Year Projects, Online Matlab Projects Tags: academic projects, Android project 2013-2014, Android project Abstract, Android project list, btech projects, dotnet project 2013-2014, dotnet project Abstract, dotnet project list, elysium technologies abstract, elysium technologies chennai, elysium technologies coimbatore, elysium technologies company, elysium technologies courses, elysium technologies erode, elysium technologies inpant traning, elysium technologies internship, elysium technologies jobs, elysium technologies madurai, elysium technologies mou, elysium technologies pondychery, elysium technologies projectlist, elysium technologies projects, elysium technologies ramnad, elysium technologies salem, elysium technologies software, elysium technologies tirunelveli, elysium technologies trichy, Final Year Projects, java project list, java projects 2013-2014, java projects Abstract, madurai software company, matlab project 2013-2014, matlab project Abstract, matlab project list, mtech projects, phd research work, Php project 2013-2014, Php project Abstract, Php project list, Power Electronic project 2013-2014, Power Electronic project Abstract, Power Electronic project list, project center Bangalore, project center chennai, project center coimbatore, project center Erode, project center Hyderabad, project center Kollam, project center madurai, project center Pandicherry, project center ramnad, project center Salem, project center Tiruneveli, project center trichy, research center, Students Projects, Vlsi project 2013-2014, Vlsi project Abstract, Vlsi project list
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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

Abstract— Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through. In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, < Final Year Projects > the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance.

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