FPGA

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Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC
₹5,500.00

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Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
₹4,500.00

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Assessing the Suitability of King Topologies for Interconnection Networks
₹5,500.00

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Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier
₹5,500.00

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Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers
₹5,500.00

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Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array
₹5,500.00

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CMCS: Current-Mode Clock Synthesis
₹5,500.00

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CMOS Integrated Time-Mode Temperature Sensor for Self-Refresh Control in DRAM Memory Cell
₹5,500.00

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Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding
₹4,500.00

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Comments on and corrections to unified VLSI architecture for photo core transform used in JPEG XR’
₹5,500.00

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Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance
₹5,500.00

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Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications
₹5,500.00

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FPGA

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

Assessing the Suitability of King Topologies for Interconnection Networks

Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

CMCS: Current-Mode Clock Synthesis

CMOS Integrated Time-Mode Temperature Sensor for Self-Refresh Control in DRAM Memory Cell

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

Comments on and corrections to unified VLSI architecture for photo core transform used in JPEG XR’

Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance

Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications

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FPGA

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

Share on:

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

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Assessing the Suitability of King Topologies for Interconnection Networks

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Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Share on:

Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers

Share on:

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

Share on:

CMCS: Current-Mode Clock Synthesis

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CMOS Integrated Time-Mode Temperature Sensor for Self-Refresh Control in DRAM Memory Cell

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Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

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Comments on and corrections to unified VLSI architecture for photo core transform used in JPEG XR’

Share on:

Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance

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Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications

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