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Home / programming language / FPGA / Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC
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Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

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SKU: PROJ7081 Categories: 2017 Projects, FPGA, VLSI Tags: Android Project, Asp.Net Project, C# Project, Computer Engineering Final Year Projects, Computer Science Final Year Projects, Electronics Projects Engineering Students Final Year, Engineering Student Project Ideas, Final Semester Projects, Final Year Project Center, Final Year Projects, ieee ECE Projects, ieee EEE Projects, ieee Final Year Projects, IEEE Projects, ieee Projects Networking, Image Processing Projects, J2EE Project, Java Project, Java Project Code, Matlab Project, PHP Project, Students Projects
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Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

Abstract— The CPGC reusable BIST engine introduced an optional hardware repair engine that works in conjunction with software to provide autorepair technology. This repair capability has been adopted by the JEDEC as a part of the WIO industry standard, known as post package repair (PPR). I n a high – volume manufacturing (HVM) environment, the automatic test equipment (ATE) can use the C P GC row hammer to detect memo r y cell defects. At the end of the detection phase of the test, the ATE test flow could initiate either a hardware automatic or a software assisted manual repair of the failed memory cells using spare row s o f t h e DR A M device. The PPR JEDEC standard has been adopted by DR AM device manufacturers. Specifically, future DR A M are built with extra spare rows of memory to compensate for the increased likelihood of memory cell failures. The automatic modes require no operator intervention, thus significantly reducing H VM test time from many minutes down to seconds. The rest of this article will be structured as follows. In Architecture of second-generation BIST engine for 14-nm SoC memor y and IO, the architecture of CPGC is presented. CPGC software infrastructure architecture details the software architecture.< final year projects >

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