0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier Abstract? A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. < final...
3D Brain Atlas Reconstruction Using Deformable Medical Image Registration: Application to Deep Brain Stimulation Surgery Abstract?In deep brain stimulation surgery the most important step is the correct location of the neurostimulator device. Here, the medical specialist needs to robustly locate the basal ganglia area (i.e. subthalamic nucleus) to implant the neurostimulator. 3D brain atlas reconstruction…
75 GBd InP-HBT MUX-DAC module for high-symbol-rate optical transmission Abstract? Owing to the spread of broadband applications, data traffic in optical communication networks is continuously increasing. High-symbol-rate optical transmission schemes with advanced multi-level modulation formats, such as M-ary quadrature amplitude modulation (QAM), are now being investigated as to their suitability for future cost-effective 1 Tb/s-class…
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 ? m CMOS Technology for Implantable Medical Applications Abstract? A 0.45-V low-power 0.18 ?m CMOS OOK/FSK RF receiver for implantable medical applications is proposed. The re-ceiver utilizes a wake-up mechanism to adjust its power consumption automatically by reading the amplitude of the input wireless OOK/FSK modulated RF…
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process Abstract?a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a…
A 40?170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS Abstract? A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplifier (PA) is described. A PLL-based architecture is employed, which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which…
A Bottom-Up Approach for Pancreas Segmentation Using Cascaded Superpixels and (Deep) Image Patch Labeling Abstract? Robust organ segmentation is a prerequisite for computer-aided diagnosis, quantitative imaging analysis, pathology detection, and surgical assistance. For organs with high anatomical variability (e.g., the pancreas), previous segmentation approaches report low accuracies, compared with well-studied organs, such as the liver…
A Combinatorial Auction Mechanism for Multiple Resource Procurement in Cloud Computing Abstract? In hybrid cloud computing, cloud users have the ability to procure resources from multiple cloud vendors, and furthermore also the option of selecting different combinations of resources. The problem of procuring a single resource from one of many cloud vendors can be modeled…
A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators Abstract? A one-pin mode transition circuit that addresses the issues related to clock synchronization in switching regulators during the mode transitions between external timing resistor and external clock. The proposed circuit reduces the circuit complexity needed to achieve mode transition during…
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability Abstract?Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. < final year projects > [numbers_sections number=”1″…
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing Abstract? Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient memory access. In this paper, we propose a configurable parallel architecture to improve the computing efficiency of integral histogram. Based on the…
A Context-Aware Architecture Supporting Service Availability in Mobile Cloud Computing Abstract? Mobile systems are gaining more and more importance, and new promising paradigms like Mobile Cloud Computing are emerging. Mobile Cloud Computing provides an infrastructure where data storage and processing could happen outside the mobile node. Specifically, there is a major interest in the use…
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