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Home / programming language / FPGA / A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

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SKU: PROJ7088 Categories: 2017 Projects, FPGA, VLSI Tags: Android Project, Asp.Net Project, C# Project, Computer Engineering Final Year Projects, Computer Science Final Year Projects, Electronics Projects Engineering Students Final Year, Engineering Student Project Ideas, Final Semester Projects, Final Year Project Center, Final Year Projects, ieee ECE Projects, ieee EEE Projects, ieee Final Year Projects, IEEE Projects, ieee Projects Networking, Image Processing Projects, J2EE Project, Java Project, Java Project Code, Matlab Project, PHP Project, Students Projects
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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

Abstract— Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient memory access. In this paper, we propose a configurable parallel architecture to improve the computing efficiency of integral histogram. Based on the configurable design in the architecture, multiple integral objects for integral histogram image, such as image intensity, image gradient, and local binary pattern, are well supported. Meanwhile, by means of the proposed strip-based memory partitioning mechanism, this architecture processes the integral histogram quickly with maximal parallelism in a pipeline manner. Besides, in this architecture, the proposed data correlation memory compression mechanism effectively solves the expansion problem of integral histogram memory caused by storing the histogram data. It fully reduces the data redundancy in the integral histograms, and saves a lot of memory resources. Experiments using Cyclone IV-based field-programmable gate array platform and 65-nm technology-based post synthesis show that our architecture improves the average computing speed by 8. 6 times with high power efficiency compared with the state-of-the-art works. < final year projects >

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