A 14-bit 250 MS/s IF Sampling Pipelined
ADC in 180 nm CMOS Process
Abstract—a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its
linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. < final year projects >
