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Home / Final Year Projects / A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process
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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

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SKU: PROJ7309 Categories: 2017 Projects, Final Year Projects, VLSI Tags: Android Project, Asp.Net Project, C# Project, Computer Engineering Final Year Projects, Computer Science Final Year Projects, Electronics Projects Engineering Students Final Year, Engineering Student Project Ideas, Final Semester Projects, Final Year Project Center, Final Year Projects, ieee ECE Projects, ieee EEE Projects, ieee Final Year Projects, IEEE Projects, ieee Projects Networking, Image Processing Projects, J2EE Project, Java Project, Java Project Code, Matlab Project, PHP Project, Students Projects
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A 14-bit 250 MS/s IF Sampling Pipelined
ADC in 180 nm CMOS Process

Abstract—a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its
linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. < final year projects >

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