FPGA

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Achieving Optimal Efficiency in Energy Transfer to a CMOS Fully Integrated Wireless Power Receiver
₹5,500.00

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Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes
₹5,500.00

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An Active Marchand Balun and Its Application to a 24-GHz CMOS Mixer
₹5,500.00

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An Area and Power Efficient Adder-Based Stepwise Linear Interpolation for Digital Signal Processing
₹5,500.00

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An Efficient File Hierarchy Attribute-Based Encryption Scheme in Cloud Computing
₹5,500.00

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An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
₹5,500.00

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An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer
₹5,500.00

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An Efficient Reverse Converter for the Three-Moduli Set ( 2 n +1 − 1 , 2 n, 2n − 1)
₹4,500.00

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An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation
₹4,500.00

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An Improved Direct Digital Converter for Bridge-Connected Resistive Sensors
₹4,500.00

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Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS
₹5,500.00

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Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
₹4,500.00

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FPGA

Achieving Optimal Efficiency in Energy Transfer to a CMOS Fully Integrated Wireless Power Receiver

Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes

An Active Marchand Balun and Its Application to a 24-GHz CMOS Mixer

An Area and Power Efficient Adder-Based Stepwise Linear Interpolation for Digital Signal Processing

An Efficient File Hierarchy Attribute-Based Encryption Scheme in Cloud Computing

An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors

An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer

An Efficient Reverse Converter for the Three-Moduli Set ( 2 n +1 − 1 , 2 n, 2n − 1)

An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation

An Improved Direct Digital Converter for Bridge-Connected Resistive Sensors

Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

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CUSTOMER SUPPORT

FPGA

Achieving Optimal Efficiency in Energy Transfer to a CMOS Fully Integrated Wireless Power Receiver

Share on:

Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes

Share on:

An Active Marchand Balun and Its Application to a 24-GHz CMOS Mixer

Share on:

An Area and Power Efficient Adder-Based Stepwise Linear Interpolation for Digital Signal Processing

Share on:

An Efficient File Hierarchy Attribute-Based Encryption Scheme in Cloud Computing

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An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors

Share on:

An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer

Share on:

An Efficient Reverse Converter for the Three-Moduli Set ( 2 n +1 − 1 , 2 n, 2n − 1)

Share on:

An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation

Share on:

An Improved Direct Digital Converter for Bridge-Connected Resistive Sensors

Share on:

Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS

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Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

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