Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
Abstract— Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. A reliable low-power multiplier design by adopting algorithmic noise tolerant ANT architecture with the ﬁxed-width multiplier to build the reduced precision replica redundancy block (RPR). < Final Year Project 2016 >The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efﬁciency. We design the ﬁxed-width RPR with error compensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simpliﬁed. In a 12 × 12 bit ANT multiplier, circuit area in our ﬁxed-width RPR can be lowered by 44.55% and power consumption in our ANT design can be saved by 23% as compared with the state-of-art ANT design.
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