A Power-Efficient Continuous-Time Incremental
Sigma-Delta ADC for Neural Recording Systems
Abstract— An analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline conﬁguration, the proposed ADC can achieve high-resolution without sacriﬁcing the conversion rate. This two-step architecture is also power-efﬁcient, as the resolution requirement for the incremental sigma-delta ADC in each step is signiﬁcantly relaxed. To further enhance the power efﬁciency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 µm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 µW, which corresponds to a ﬁgure-of-merit of 0.85 pJ/conv.
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