A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification
Abstract—A parallel digital VLSI architecture for combined support vector machine < Final Year Projects 2016 > SVM training and classiﬁcation. For the ﬁrst time, cascade SVM, a powerful training algorithm, is leveraged to signiﬁcantly improve the scalability of hardware-based SVM training and develop an efﬁcient parallel VLSI architecture. The presented architecture achieves excellent scalability by spreading the training workload of a given data set over multiple SVM processing units with minimal communication overhead. Hardware-friendly implementation of the cascade algorithm is employed to achieve low hardware overhead and allow for training over data sets of variable size.In the proposed parallel cascade architecture, a multilayer system bus and multiple distributed memories are used to fully exploit parallelism.