Product Description
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC
Abstract— An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC. A two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. < Final Year Project 2016 >The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standard’s filter while designing a root-raised-cosine finite-impulse response filter for multistandard DUC for three different standards. In the next step, a 2-bit binary common subexpression BCS -based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter.
Including Packages
Our Specialization
Support Service
Statistical Report
![An Efficient Vlsi Architecture Of A Reconfigurable Pulse-Shaping Fir Interpolation Filter For Multistandard Duc 5 110](https://myprojectbazaar.com/wp-content/uploads/2013/12/110.jpg)
satisfied customers
3,589![An Efficient Vlsi Architecture Of A Reconfigurable Pulse-Shaping Fir Interpolation Filter For Multistandard Duc 6 25](https://myprojectbazaar.com/wp-content/uploads/2013/12/25.jpg)
Freelance projects
983![An Efficient Vlsi Architecture Of A Reconfigurable Pulse-Shaping Fir Interpolation Filter For Multistandard Duc 7 311](https://myprojectbazaar.com/wp-content/uploads/2013/12/311.jpg)
sales on Site
11,021![An Efficient Vlsi Architecture Of A Reconfigurable Pulse-Shaping Fir Interpolation Filter For Multistandard Duc 8 41](https://myprojectbazaar.com/wp-content/uploads/2013/12/41.jpg)
developers
175+
There are no reviews yet