An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC
Abstract— An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC. A two-step optimization technique for designing a reconﬁgurable VLSI architecture of an interpolation ﬁlter for multistandard digital up converter (DUC) to reduce the power and area consumption. < Final Year Project 2016 >The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standard’s ﬁlter while designing a root-raised-cosine ﬁnite-impulse response ﬁlter for multistandard DUC for three different standards. In the next step, a 2-bit binary common subexpression BCS -based BCS elimination algorithm has been proposed to design an efﬁcient constant multiplier, which is the basic element of any ﬁlter.
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