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VLSI
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A 65 nm Cryptographic Processor for High Speed Pairing Computation
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A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC
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A CMOS Ultrawideband Pulse Generator for 3–5 GHz Applications
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A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
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A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators
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A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme
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A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability
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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
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A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
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A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
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A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic
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A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
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