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Home
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VLSI
/ Page 17
Timing Error Tolerance in Small Core Designs for SoC Applications
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Transactions Briefs Computing Seeds for LFSR-Based Test Generation From Nontest Cubes
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Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing
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Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM
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Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
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Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
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Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product
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Unified VLSI architecture for photo core transform used in JPEG XR
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Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications
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VLSI Architecture for delay efficient 32-bit Multiplier using Vedic Mathematic sutras
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VLSI Computational Architectures for the Arithmetic Cosine Transform
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VLSI Design for SVM-Based Speaker Verification System
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