Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
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Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
Abstract— Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were −8.6 and −21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9–122.2 and 122.7–122.9 GHz for PLL1 and PLL2. The in-band phase noises were −59.2 and −60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were −102.4 and −99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000× 760 µ m2 (PLL1) and 1300 × 840 µ m2 (PLL2) including probing pads. < final year projects >
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