VLSI Design for SVM-Based Speaker Verification System
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VLSI Design for SVM-Based Speaker Verification System
Abstract— VLSI Design for SVM-Based Speaker Verification System. The chip implementation of a support vector machine (SVM)-based speaker verification system. The proposed chip comprises a speaker feature extraction SFE module, an SVM module, and a decision module. < Final Year Project 2016 >The SFE module performs autocorrelation analysis, linear predictive coefficient (LPC) extraction, and LPC-to-cepstrum conversion. The SVM module includes a Gaussian kernel unit and a scaling unit. The purpose of the Gaussian kernel unit is first to evaluate the kernel value of a test vector and a support vector. Four Gaussian kernel processing elements (GK-PEs) are designed to process four support vectors simultaneously. Each GK-PE is designed in the pipeline fashion and is capable of performing 2-norm and exponential operations.
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