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Home / Final Year Projects / Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell
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VLSI Project - FPGA
  • VLSI Project - FPGA

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

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SKU: PROJ7334 Categories: 2017 Projects, Final Year Projects, VLSI Tags: Android Project, Asp.Net Project, C# Project, Computer Engineering Final Year Projects, Computer Science Final Year Projects, Electronics Projects Engineering Students Final Year, Engineering Student Project Ideas, Final Semester Projects, Final Year Project Center, Final Year Projects, ieee ECE Projects, ieee EEE Projects, ieee Final Year Projects, IEEE Projects, ieee Projects Networking, Image Processing Projects, J2EE Project, Java Project, Java Project Code, Matlab Project, PHP Project, Students Projects
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Single-Ended Schmitt-Trigger-Based
Robust Low-Power SRAM Cell

Abstract— a Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read
and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and temperature variations on various performance parameters, such as hold SNM, read SNM, write margin, immunity to half-select issue, ION/IOFF ratio of reading path, and leakage power of the cell; Monte Carlo simulation results confirm the robustness of the proposed cell toward these issues. Layout drawn in a 45-nm technology rule shows that the proposed cell occupies 2.02× greater area as compared with 6T SRAM cells. However,
6.9× higher ION/IOFF ratio of the read path of the proposed cell as compared with 6T cell holds potential to significantly subside the area overhead.< final year projects >

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