A Short-Channel-Effect-Degraded Noise Margin Model for Junctionless Double-Gate MOSFET Working on Subthreshold CMOS Logic Gates
Product Description
A Short-Channel-Effect-Degraded Noise Margin Model for Junctionless Double-Gate MOSFET Working on Subthreshold CMOS Logic Gates
Abstract— Based on the device and equivalent transistor model, we present a short-channel-effect (SCE)-degraded noise margin (NM) model for junctionless double-gate MOSFET working on subthreshold CMOS logic gate. < final year projects >
Including Packages
Our Specialization
Support Service
Statistical Report
satisfied customers
3,589
Freelance projects
983
sales on Site
11,021
developers
175+
Additional Information
| Domains |
|---|
