Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs
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Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs
Abstract—Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized bitline scheme to eliminate the leakage dependence on data pattern and thus improves RBL sensing and its resilience against process, voltage, and temperature variations. < final year projects >
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