Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Abstract— Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to anew enhanced version, exVAR-TX, to minimize and predict the power/energy and power/energy variability of a 16-nm 6T-SRAM under the influence of the three major types of variations: Fabrication, Operation, and Implementation. Using exVAR-TX for architectural optimization [exhaustively computing and comparing the range of feasible architectures subject to interdie (die-to-die/D2D) and intradie (within-die/WID) process and operation variations (PVT), electromigration (EM), negative bias temperature instability (NBTI), and soft-errors, among others] on top of deploying the most recent state of the art effective mitigation techniques we show that energy and energy-delay-product (EDP) of 64KB 16-nm 6T-SRAM could be reduced by 12.5X and 33%, respectively, as compared to the existing conventional designs. As in most of the arena of digital design, reduction of power dissipation in memories is becoming of premier importance. Memory designers have been remarkably good in keep-ing dissipation in check, even while increasing the memory capacity with about 10 orders of magnitude over the last 40Cyears. Yet, the challenges are mounting. The primary goal of low-power high-speed circuit design differs from application to application. In case of battery operated portable systems, such as cellular phones and laptops, the primary goal is to keep the battery lifetime and weight reasonable. < final year projects >