Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

Abstract— The design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112-mm 2 area and consumed 2.78- µ W power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset. The implantable cardioverter-defibrillator has been con-sidered as the best protection against sudden death from ventricular arrhythmias in high-risk individuals. However, most sudden deaths occur in individuals who do not have high-risk profiles. Long-term ECG monitoring is the criterion standard for the diagnosis of ventricular arrhythmia. < final year projects >