Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
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Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
Abstract—This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. < final year projects >
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