Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Abstract— Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. Behavior of adiabatic logic circuits in weak inversion or sub threshold regime is analyzed in depth for the first time in the literature to make great improvement in ultra-low power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder < Final Year Projects 2016 > CLA has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on sub threshold adiabatic logic-based 4-bit CLA has also been addressed separately. Post layout simulations show that sub threshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.