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Home / Final Year Projects / Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design
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Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

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SKU: PROJ7325 Categories: 2017 Projects, Final Year Projects, VLSI Tags: Android Project, Asp.Net Project, C# Project, Computer Engineering Final Year Projects, Computer Science Final Year Projects, Electronics Projects Engineering Students Final Year, Engineering Student Project Ideas, Final Semester Projects, Final Year Project Center, Final Year Projects, ieee ECE Projects, ieee EEE Projects, ieee Final Year Projects, IEEE Projects, ieee Projects Networking, Image Processing Projects, J2EE Project, Java Project, Java Project Code, Matlab Project, PHP Project, Students Projects
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Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

Abstract— As the circuit complexity increases, the number of internal nodes increases proportionally, and individual internal nodes are less accessible due to the limited number of available I/O pins. To address the problem, we proposed power line communications (PLCs) at the IC level, specifically the dual use
of power pins and power distribution networks for application/ observation of test data as well as delivery of power. A PLC receiver presented in this paper intends to demonstrate the proof of concept, specifically the transmission of data through power lines. The main design objective of the proposed PLC receiver is the robust operation under variations and droops of the supply voltage rather than high data speed.< final year projects >

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