High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2 m )

Abstract— An efficient pipelined architecture of elliptic curve scalar multiplication (ECSM) over GF(2M ). The architecture uses a bit-parallel finite-field (FF) multiplier accumulator (MAC) based on the Karatsuba–Ofman algorithm. The Montgomery ladder algorithm is modified for better sharing of execution paths. The data path in the architecture is well designed, so that the critical path contains few extra logic primitives apart from the FF MAC. In order to find the optimal number of pipeline stages, scheduling schemes with different pipeline stages are proposed and the ideal placement of pipeline registers is thoroughly analyzed. We implement ECSM over the five binary fields recommended by the National Institute of Standard and Technology on Xilinx Virtex-4 and Virtex-5 field-programmable gate arrays. The three-stage pipelined architecture is shown to have the best performance, which achieves a scalar multiplication over GF(2 163 )in6.1 µ s using 7354 Slices on Virtex-4. Using Virtex-5, the scalar multiplication for m = 163, 233, 283, 409, and 571 can be achieved in 4.6, 7.9, 10.9, 19.4, and 36.5 µ s, respectively, which are faster than previous results. ECC over binary field GF(2 m )is especially attractive for its carry-free property [2]. However, for resource-constrained platforms such as field-programmable ate arrays (FPGAs), it remains a challenge to achieve high performance as well as area efficient designs of ECC< final year projects >