Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories
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Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories
Abstract— The need to meet power-performance-area (PPA) con-strains in static random access memory (SRAM) memory modules and the continuous search for growing storing densities have reduced the value of the voltage variation that a single memory cell can induce on the attached bit-line in an acceptable accessing time. < final year projects >
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