A 40–170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS
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A 40–170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS
Abstract— A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplifier (PA) is described. A PLL-based architecture is employed, which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used in pulsewidth modulation (PWM) generation. < final year projects >
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