Showing all 6 results
A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories Abstract-Bias temperature instability (BTI) is known as one serious reliability concern in nanoscale technologies. BTI gradually increases the absolute value of threshold voltage (Vth) of MOS transistors. The main consequence of Vth shift of the SRAM cell transistors is the static noise margin (SNM) degradation. The…
A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design Abstract-Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select…
An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation Abstract-To achieve the goal of secure communication,cryptography is an essential operation. Many applications, including health-monitoring and biometric data based recognition system, need short-term data security. To design short-term security based applications, there is an essential need of high-performance, low cost and area-efficient VLSI…
Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding Abstract-Globalization of microchip fabrication opens the possibility for an attacker to insert hardware Trojans into a chip during the manufacturing process. While most defensive methods focus on detection or prevention, a recent method, called Randomized Encoding of Combinational Logic for…
Low Power Address Generator for Memory Built-In Self Test Abstract-Memory is one of the basic computer components that is intensively accessed. Therefore, it is more likely to be affected by manufacturing faults rather than other components in the System on Chip (SoC). Memory Built-in Self Test (MBIST) is the most commonly used to test embedded…
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates Abstract-In this paper, novel circuits for XOR/XNOR and simultaneous XOR?XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six…
End of content
End of content
Don't have an account yet? Sign up
No items in your cart. Go on, fill it up with something you love!
Start Shopping Now
Free 
