Showing 1–12 of 99 results
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage Abstract– We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged…
28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression Abstract-With the development of modern semiconductor fabrication technology, the channel length of the CMOS device and the device pitch continually shrink accompanied by more and more severe process variation and signal coupling effect, respectively. In this paper, we explain how the coupling effect interferes with the action…
75 GBd InP-HBT MUX-DAC module for high-symbol-rate optical transmission Abstract? Owing to the spread of broadband applications, data traffic in optical communication networks is continuously increasing. High-symbol-rate optical transmission schemes with advanced multi-level modulation formats, such as M-ary quadrature amplitude modulation (QAM), are now being investigated as to their suitability for future cost-effective 1 Tb/s-class…
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 ? m CMOS Technology for Implantable Medical Applications Abstract? A 0.45-V low-power 0.18 ?m CMOS OOK/FSK RF receiver for implantable medical applications is proposed. The re-ceiver utilizes a wake-up mechanism to adjust its power consumption automatically by reading the amplitude of the input wireless OOK/FSK modulated RF…
A 32 kb 0.35?1.2 V, 50 MHz?2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS Abstract-An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35?1.2 V at all process corners. A differential read asymmetric…
A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC Abstract-In this paper, we propose a time-based analog-to digital converter (ADC) architecture combining a ?ash ADC and vernier time-to-digital converter (TDC) to achieve both high speed and high resolution. The ?ash ADC and vernier TDC are pipelined to increase the conversion speed. A…
Automobile Spare Shop(Android App) Abstract-A low-power ultrawideband (UWB) pulse generator based on pulsed oscillator architecture for 3?5 GHz applications is proposed. The pulsed oscillator is improved, so it realizes binary phase shift keying (BPSK) modulation. Unlike ON?OFF keying or pulse-position modulation (PPM), BPSK can scramble the spectrum, so it can be used in high pulse…
A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators Abstract? A one-pin mode transition circuit that addresses the issues related to clock synchronization in switching regulators during the mode transitions between external timing resistor and external clock. The proposed circuit reduces the circuit complexity needed to achieve mode transition during…
A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme Abstract-Previous 6T SRAMs commonly employ a wordline voltage underdrive (WLUD) scheme to suppress half-select (HS) disturbs in read and write cycles, at the expense of reduced cell read current ( I CELL ) and degraded write…
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing Abstract? Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient memory access. In this paper, we propose a configurable parallel architecture to improve the computing efficiency of integral histogram. Based on the…
A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic Abstract? A high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in…
A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories Abstract-Bias temperature instability (BTI) is known as one serious reliability concern in nanoscale technologies. BTI gradually increases the absolute value of threshold voltage (Vth) of MOS transistors. The main consequence of Vth shift of the SRAM cell transistors is the static noise margin (SNM) degradation. The…
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