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Home
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VLSI
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Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
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Hard-Information Bit-Reliability Based Decoding Algorithm for Majority-Logic Decodable Nonbinary LDPC Codes
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Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers
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High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
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High- Throughput Area – Efficient Processor for Cryptography
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High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2 m )
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High-Sensitivity CMOS RF-DC Converter in HF RFID Band
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High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
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High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
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Hybrid LUT/Multiplexer FPGA Logic Architectures
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Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
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Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures
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