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Home
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programming language
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FPGA
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Recursive Approach to the Design of a Parallel Self-Timed Adder
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Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
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Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches
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RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
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Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors
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Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process
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Stable, Reliable and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-design
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Stable, Reliable and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-design
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Timing Error Tolerance in Small Core Designs for SoC Applications
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Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
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Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
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Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications
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