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High-Sensitivity CMOS RF-DC Converter in HF RFID Band
₹5,500.00

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High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
₹5,500.00

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High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
₹4,500.00

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High-Throughput Low-Energy Self timed CAM Based on Reordered Overlapped Search Mechanism
₹4,500.00

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Hybrid Energy Efficient Distributed Protocol forHeterogeneous Wireless Sensor Network
₹4,500.00

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Hybrid LUT/Multiplexer FPGA Logic Architectures
₹5,500.00

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Implementation of Fixed and Floating Point Square Root Using Nonrestoring Algorithm on FPGA
₹4,500.00

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Implementation of Low Power 8-Bit Multiplier using Gate Diffusion Input Logi
₹4,500.00

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Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
₹4,500.00

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Improve the Performance of LRU Page Replacement Algorithm using Augmentation of DatRobust Secure Scan Design Against Scan-Based Differential Cryptanalysis Structure
₹4,500.00

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Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions
₹4,500.00

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Improvement in Power Factor & THD Using Dual Boost Converter
₹4,500.00

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VLSI

High-Sensitivity CMOS RF-DC Converter in HF RFID Band

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

High-Throughput Low-Energy Self timed CAM Based on Reordered Overlapped Search Mechanism

Hybrid Energy Efficient Distributed Protocol forHeterogeneous Wireless Sensor Network

Hybrid LUT/Multiplexer FPGA Logic Architectures

Implementation of Fixed and Floating Point Square Root Using Nonrestoring Algorithm on FPGA

Implementation of Low Power 8-Bit Multiplier using Gate Diffusion Input Logi

Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Improve the Performance of LRU Page Replacement Algorithm using Augmentation of DatRobust Secure Scan Design Against Scan-Based Differential Cryptanalysis Structure

Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

Improvement in Power Factor & THD Using Dual Boost Converter

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CUSTOMER SUPPORT

VLSI

High-Sensitivity CMOS RF-DC Converter in HF RFID Band

Share on:

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Share on:

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

Share on:

High-Throughput Low-Energy Self timed CAM Based on Reordered Overlapped Search Mechanism

Share on:

Hybrid Energy Efficient Distributed Protocol forHeterogeneous Wireless Sensor Network

Share on:

Hybrid LUT/Multiplexer FPGA Logic Architectures

Share on:

Implementation of Fixed and Floating Point Square Root Using Nonrestoring Algorithm on FPGA

Share on:

Implementation of Low Power 8-Bit Multiplier using Gate Diffusion Input Logi

Share on:

Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Share on:

Improve the Performance of LRU Page Replacement Algorithm using Augmentation of DatRobust Secure Scan Design Against Scan-Based Differential Cryptanalysis Structure

Share on:

Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

Share on:

Improvement in Power Factor & THD Using Dual Boost Converter

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