Showing 13–24 of 3870 results
3-D Face Recognition Under Occlusion Using Masked Projection Abstract?With advances in sensor technology, the three-dimensional (3-D) face has become an emerging biometric modality, preferred especially in high security applications. However, dealing with occlusions covering the facial surface is a great challenge, which should be handled to enable applicability to fully automatic security systems. In this…
3D Brain Atlas Reconstruction Using Deformable Medical Image Registration: Application to Deep Brain Stimulation Surgery Abstract?In deep brain stimulation surgery the most important step is the correct location of the neurostimulator device. Here, the medical specialist needs to robustly locate the basal ganglia area (i.e. subthalamic nucleus) to implant the neurostimulator. 3D brain atlas reconstruction…
75 GBd InP-HBT MUX-DAC module for high-symbol-rate optical transmission Abstract? Owing to the spread of broadband applications, data traffic in optical communication networks is continuously increasing. High-symbol-rate optical transmission schemes with advanced multi-level modulation formats, such as M-ary quadrature amplitude modulation (QAM), are now being investigated as to their suitability for future cost-effective 1 Tb/s-class…
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 ? m CMOS Technology for Implantable Medical Applications Abstract? A 0.45-V low-power 0.18 ?m CMOS OOK/FSK RF receiver for implantable medical applications is proposed. The re-ceiver utilizes a wake-up mechanism to adjust its power consumption automatically by reading the amplitude of the input wireless OOK/FSK modulated RF…
A 0.45-V, 14.6-nW CMOS Subthreshold Voltage Reference With No Resistors and No BJTs Abstract?A low-voltage low-power CMOS sub-threshold voltage reference with no resistors and no bipolar junction transistors in a wide temperature range. The temperature stability is improved by second-order compensation. By employing a bulk-driven technique and the< Final Year Projcts 2016 > MOS transistors…
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process Abstract?a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a…
A 16 Kb Spin-Transfer Torque Random Access Memory With Self-Enable Switching and Precharge Sensing Schemes Abstract?Spin-transfer torque magnetic random access memory (STT-MRAM) is considered one of the most promising non-volatile memory candidates thanks to its excellent performance in terms of access speed, endurance, and compatibility to CMOS. However, high power supply voltage is required in…
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme Abstract? A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme. A 3.5 GS/s 6-bit current-steering digital-to-analog converter DAC with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC…
A 2D Discrete Wavelet Transform Based 7- State Hidden Markov Model for Efficient Face Recognition Abstract? A 2D Discrete Wavelet Transform Based 7- State Hidden Markov Model for Efficient Face Recognition. Video View Demo [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation Slides Flow Diagram Database File Screenshots Execution Procedure…
A 32 kb 0.35?1.2 V, 50 MHz?2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS Abstract-An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35?1.2 V at all process corners. A differential read asymmetric…
A 40?170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS Abstract? A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplifier (PA) is described. A PLL-based architecture is employed, which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which…
A 6 b 5 GS/s 4 Interleave d 3 b/Cycle SAR ADC Abstract?This paper presents a 4? time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b /cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls…
End of content
End of content
Don't have an account yet? Sign up
No items in your cart. Go on, fill it up with something you love!
Start Shopping Now
