FPGA

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Low-Computing-Load, High-Parallelism Detection Method based on Chebyshev Iteration for Massive MIMO Systems with VLSI Architecture
₹4,500.00

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Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
₹4,500.00

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Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop
₹5,500.00

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Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
₹5,500.00

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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
₹5,500.00

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Low‑power half‑select free single‑ended 10 transistor SRAM cell
₹5,500.00

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LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
₹5,500.00

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Modeling and Design of EMI-Immune OpAmps in 0.18-μ m CMOS Technology
₹5,500.00

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Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells
₹4,500.00

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Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM
₹4,500.00

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Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology
₹4,500.00

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Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter
₹5,500.00

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FPGA

Low-Computing-Load, High-Parallelism Detection Method based on Chebyshev Iteration for Massive MIMO Systems with VLSI Architecture

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme

Low‑power half‑select free single‑ended 10 transistor SRAM cell

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

Modeling and Design of EMI-Immune OpAmps in 0.18-μ m CMOS Technology

Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology

Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter

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FPGA

Low-Computing-Load, High-Parallelism Detection Method based on Chebyshev Iteration for Massive MIMO Systems with VLSI Architecture

Share on:

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

Share on:

Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop

Share on:

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

Share on:

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme

Share on:

Low‑power half‑select free single‑ended 10 transistor SRAM cell

Share on:

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

Share on:

Modeling and Design of EMI-Immune OpAmps in 0.18-μ m CMOS Technology

Share on:

Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells

Share on:

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM

Share on:

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology

Share on:

Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter

Share on:

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