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Home / Final Year Projects / 2013 Projects / Fault based Test Minimization Using Genetic Algorithm for Two Stage Combinational Circuits
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Fault based Test Minimization Using Genetic Algorithm for Two Stage Combinational Circuits

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SKU: PROJ1439 Categories: 2013 Projects, 2014 Projects, Final Year Projects Tags: academic projects, Android project 2013-2014, Android project Abstract, Android project list, btech projects, dotnet project 2013-2014, dotnet project Abstract, dotnet project list, elysium technologies abstract, elysium technologies chennai, elysium technologies coimbatore, elysium technologies company, elysium technologies courses, elysium technologies erode, elysium technologies inpant traning, elysium technologies internship, elysium technologies jobs, elysium technologies madurai, elysium technologies mou, elysium technologies pondychery, elysium technologies projectlist, elysium technologies projects, elysium technologies ramnad, elysium technologies salem, elysium technologies software, elysium technologies tirunelveli, elysium technologies trichy, Final Year Projects, java project list, java projects 2013-2014, java projects Abstract, madurai software company, matlab project 2013-2014, matlab project Abstract, matlab project list, mtech projects, phd research work, Php project 2013-2014, Php project Abstract, Php project list, Power Electronic project 2013-2014, Power Electronic project Abstract, Power Electronic project list, project center Bangalore, project center chennai, project center coimbatore, project center Erode, project center Hyderabad, project center Kollam, project center madurai, project center Pandicherry, project center ramnad, project center Salem, project center Tiruneveli, project center trichy, research center, Students Projects, Vlsi project 2013-2014, Vlsi project Abstract, Vlsi project list
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Fault based Test Minimization Using Genetic Algorithm for Two Stage Combinational Circuits

Abstract— Fault based Test Minimization Using Genetic Algorithm for Two Stage Combinational Circuits. The field of digital systems has undergone a major revolution in recent decades. Circuits are shrinking in physical size while growing both in speed and range of capabilities. This rapid advancement is not without serious problems, however. Especially worrisome are verification and testing, which become more important as the system complexity increases and time-to-market decreases. Genetic algorithms have been very effective when combined with deterministic algorithm for test pattern generation in digital circuits. In this paper, < Final Year Projects > single output logic circuits composed of AND, OR and XOR gates are experimented with the proposed algorithm. Time complexity is polynomial to generate the tests that detect all the stuck-at-faults in these circuits. Electronic industry is spending considerable amount of time in the diagnosis of VLSI chips. This time factor dominates in determining the overall cost of the chip. In this paper, the authors present a new genetic algorithm to minimize test patterns for combinational circuits. The fault-detection problem in combinational circuits is formulated in a new framework. In the proposed work, evolutionary principles are employed in test minimization stage alone. Test minimization stage is cumbersome in deterministic and heuristic methods. Results show that test sets generated using the evolutionary approach are more compact than those generated by earlier approaches for many circuits. The proposed genetic algorithm uses boolean functions in Sum-of-Products form. The authors implemented this algorithm in C programming code. The test patterns generated for boolean functions with considerable number of gates are found to be compact and the results are encouraging.

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