Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
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Design-Efficient Approximate Multiplication
Circuits Through Partial Product Perforation
Abstract— Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error tolerant applications. In this paper, we focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. We prove in a mathematically rigorous manner that in partial product perforation, the imposed errors are bounded and predictable, depending only on the input distribution. Through extensive experimental evaluation, we apply the partial product perforation method on different multiplier architectures and expose the optimal architecture– perforation configuration pairs for different error constraints.< final year projects >
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