A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme

Abstract-Previous 6T SRAMs commonly employ a wordline voltage underdrive (WLUD) scheme to suppress half-select (HS) disturbs in read and write cycles, at the expense of reduced cell read current ( I CELL ) and degraded write margin (WM). At the same time, proposes the dual-split-control (DSC) scheme, including split WLs and split cell VSS (CVSS), for 6T SRAM to maintain a compact cell area and improve HS cell stability during the read and write cycles without degrading I CELL and WM. A segmented CVSS-strapping scheme is developed to suppress the ground bounce on the split-CVSS lines by using VLSI Method. In addition, the CVSS voltage for S6T can be generated by either a constant voltage source or a charge-sharing-based CVSS generation scheme. As a result, 28-nm 256-kb DSC6T SRAM macro was fabricated and achieves a 280-mV lower VDDmin than a conventional 6T SRAM. Final year VLSI projects