Showing 73–84 of 206 results
Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation Abstract-In the first place, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed.in the same way, the complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of…
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters Abstract? Most of the research on the implementation of finite impulse response (FIR) filter so far focuses on the optimization of the multiple constant multiplication (MCM) block. But it is observed that the product-accumulation section often contributes the major part of the critical…
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation Abstract?The Booth multiplier has been widely used for high performance signed multiplication by encoding and thereby reducing the number of partial products. A multiplier using the radix-4 (or modified Booth) algorithm is very efficient due to the ease of partial product generation, whereas the radix-8 Booth…
Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC Abstract? The CPGC reusable BIST engine introduced an optional hardware repair engine that works in conjunction with software to provide autorepair technology. This repair capability has been adopted by…
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications Abstract– In the first place, the limited size and power budgets of space-bound systems often contradict the requirements for reliable circuit operation within high-radiation environments. Here the smallest solution for soft-error tolerant embedded memory yet to be presented. In addition, complementary dual-modular redundancy (CDMR)…
Assessing the Suitability of King Topologies for Interconnection Networks Abstract? In the late years many different interconnection networks have been used with two main tendencies. One is characterized by the use of high- degree routers with long wires while the other uses routers of much smaller degree. The latter rely on two- dimensional mesh and…
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier Abstract? The design of a low-voltage static random access memory (SRAM) for biomedical chip applications. The SRAM is designed using a standard 8T bit cell, featuring a shared data-aware write scheme and a differential reference-based sense amplifier. The proposed techniques make it possible for…
Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers Abstract? A self-test method for zero-IF radio frequency transceivers using primarily loopback, aided by a small built-in self-test (BIST) circuitry, to determine critical performance parameters, such as I/Q imbalance and nonlinearity coefficients. The transceiver is placed in the loopback mode by couplers, specifically designed to be…
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array Abstract? An electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. Firs t, the built-in self-test (BIST)…
CMCS: Current-Mode Clock Synthesis Abstract? In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance. New circuit approaches for current-mode (CM) clocking save significant clock power,…
Compact Conformal Map for Greedy Routing in Wireless Mobile Sensor Networks Abstract? a low-power complementary metal?oxide?semiconductor (CMOS) smart temperature sensor in order to obtain self-refresh control for low-power memory cells. The multiple-block system is composed of a temperatureto- pulse generator (TPG), a time-to-digital converter (TDC), and a frequency selector. A pulse-shrinking system with an inverter-based…
Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding Abstract-Globalization of microchip fabrication opens the possibility for an attacker to insert hardware Trojans into a chip during the manufacturing process. While most defensive methods focus on detection or prevention, a recent method, called Randomized Encoding of Combinational Logic for…
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