An Area and Power Efficient Adder-Based Stepwise Linear Interpolation for Digital Signal Processing Abstract? Linear interpolation is frequently used in digital signal processing applications to reconstruct signals, e.g., image, and audio processing, for which the multiplier and divider are two power- and area-hungry operators. Since most natural world phenomena are not exactly representable in linear…
An Area-Efficient High-Resolution Resistor-String DAC with Reverse Ordering Scheme for Active Matrix Flat-Panel Display Data Driver ICs Abstract?we propose an area-efficient high-resolution resistor-string digital-to-analog converter (R-DAC) with a reverse ordering scheme for active matrix flat-panel display data driver ICs. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation…
An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors Abstract? Chip multiprocessors (CMPs) re quire a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While pack et-switched mesh interconnects sacrifice performance of many-core processors due to NoC- induced delays, existing circuit-switched interconnects…
An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer Abstract? An efficient on-chip inductorless switching power converter for solar energy harvesting is presented. The new energy-efficient switching power converter improves the charge transfer capability as well as charge sharing time from the harvester to the load. We also present an analytical model to…
An Efficient Reverse Converter for the Three-Moduli Set ( 2 n +1 ? 1 , 2 n, 2n ? 1) Abstract– The well-known three moduli set (2 n + 1 , 2 n, 2 n ?1), where n is a positive integer, has received a considerable attention over the last three decades. Many researchers have…
An Efficient Single and Double Adjacent Error Correcting Parallel Decoder for Extended Golay Code Abstract?Memories that operate in harsh environments, like for example space, suffer a significant number of errors. The error correction codes (ECCs) are routinely used to ensure that those errors do not cause data corruption. However, ECCs introduce overheads both in terms…
An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation Abstract-To achieve the goal of secure communication,cryptography is an essential operation. Many applications, including health-monitoring and biometric data based recognition system, need short-term data security. To design short-term security based applications, there is an essential need of high-performance, low cost and area-efficient VLSI…
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC Abstract? An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC. A two-step optimization technique for designing a recon?gurable VLSI architecture of an interpolation ?lter for multistandard digital up converter (DUC) to reduce the power and area…
An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats Abstract?The design and testing of an electrode driving application speci?c integrated circuit < Final Year Projects 2016 > ASIC intended for epidural spinal cord electrical stimulation in rats. The ASIC can deliver up to 1 mA fully programmable monophasic or biphasic stimulus current pulses,…
An Improved Direct Digital Converter for Bridge-Connected Resistive Sensors Abstract-An improved direct digital converter (IDDC) suitable for bridge-connected resistive sensors is presented in this paper. In VLSI Projects, the input stage of a dual-slope analog-to-digital converter is altered to accommodate a resistive sensor bridge, as its integral part and the logic of conversion incorporate automatic…
Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS Abstract? an E-band quadrature voltagecontrolled oscillator implemented in 28-nm CMOS. Two fundamental oscillators are coupled by means of gate-to-drain transformers to realize accurate quadrature phases and switched coupled inductors are added for tuning extension. Closed-form expressions of the oscillation frequency and the…
Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology Abstract?The analysis and design of a two-stage stacked power amplifier (PA) with very broadband gain frequency response and power performance in a small chip size. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation…
