Showing 37–48 of 206 results
A New Data Transfer Method via Signal-Rich-Art Code Images Captured by Mobile Devices Abstract? A New Data Transfer Method via Signal-Rich-Art Code Images Captured by Mobile Devices. A new type of signal-rich-art image for applications of data transfer, called signal-rich-art code image, is proposed. The created code image is visually similar to a preselected target…
A New XOR-Free Approach for Implementation of Convolutional Encoder Abstract?This letter presents a new algorithm to construct an XOR-Free architecture of a power efficient Convolutional Encoder. Optimization of XOR operators is the main concern while implementing polynomials over GF(2), which consumes a significant amount of dynamic power. < final year projects > [numbers_sections number=”1″ title=”Including…
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO Abstract? Many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture…
A Novel Quantum-Dot Cellular Automata X -bit ? 32-bit SRAM Abstract? Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a…
A Novel Two-Split Capacitor Array with Linearity Analysis for High-Resolution SAR ADCs Abstract? A Novel Two-Split Capacitor Array with Linearity Analysis for High-Resolution SAR ADCs. A novel two-split capacitor < Final Year Projects 2016 > T-SC array structure for Successive Approximation Register (SAR) analog-to-digital converter (ADC) is proposed. When used as digital ?to-analog converter (DAC),…
A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification Abstract?A parallel digital VLSI architecture for combined support vector machine < Final Year Projects 2016 > SVM training and classi?cation. For the ?rst time, cascade SVM, a powerful training algorithm, is leveraged to signi?cantly improve the scalability of hardware-based SVM training and…
A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems Abstract? An analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline con?guration, the proposed ADC can achieve high-resolution without sacri?cing the conversion rate. This two-step architecture is also power-ef?cient, as the resolution requirement for the incremental…
A Power-Efficient Reconfigurable Output-Capacitor-Less Low-Drop-Out Regulator for Low-Power Analog Sensing Front-End Abstract-A power efficient reconfigurable output-capacitorless (OCL) low-drop-out (LDO) voltage regulator for low-power analog sensing front-end is proposed in this paper. This LDO consists of a floating-gate nMOS pass transistor, an adaptively biased error amplifier, and capacitive circuits for voltage reference generation and for feedback…
A Power-Efficient Signal-Specific ADC for Sensor-Interface Applications Abstract– A novel signal-specific power-efficient analog-to-digital converter (ADC) is proposed for sensorinterface applications. Instead of digitizing each analog sample independently, the proposed ADC determines the digital code corresponding to each new input sample by digitizing the difference of two consecutive samples. Therefore, for the applications with low-varying input…
An IoT Based System for Remote Patient Monitoring Abstract? Inverter-based implementation of operationaltransconductance amplifiers is an attractive approach for lowvoltage realization of analog subsystems. However, the high sensitivity of inverterlike amplifiers? performance to process and temperature variations limit the achievable performance of the whole system across process and temperature corners. In this paper, a tuning…
A Reconfigurable 5-to-14 bit SARADC for Battery-Powered Medical Instrumentation Abstract? In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters < Final Year Projects 2016 > ADCs have to be adapted to the needs of the application to avoid power wastage. This paper presents a recon?gurable successive approximation register (SAR) ADC implemented in…
A Short-Channel-Effect-Degraded Noise Margin Model for Junctionless Double-Gate MOSFET Working on Subthreshold CMOS Logic Gates Abstract? Based on the device and equivalent transistor model, we present a short-channel-effect (SCE)-degraded noise margin (NM) model for junctionless double-gate MOSFET working on subthreshold CMOS logic gate. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete…
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