A 65 nm Cryptographic Processor for High Speed Pairing Computation Abstract? A 65 nm Cryptographic Processor for High Speed Pairing Computation. Pairings are attractive and competitive cryptographic primitives for establishing various novel and powerful information security schemes. This paper presents a ?exible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels….
A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC Abstract-In this paper, we propose a time-based analog-to digital converter (ADC) architecture combining a ?ash ADC and vernier time-to-digital converter (TDC) to achieve both high speed and high resolution. The ?ash ADC and vernier TDC are pipelined to increase the conversion speed. A…
Automobile Spare Shop(Android App) Abstract-A low-power ultrawideband (UWB) pulse generator based on pulsed oscillator architecture for 3?5 GHz applications is proposed. The pulsed oscillator is improved, so it realizes binary phase shift keying (BPSK) modulation. Unlike ON?OFF keying or pulse-position modulation (PPM), BPSK can scramble the spectrum, so it can be used in high pulse…
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT Abstract? An ef?cient combined single-path delay commutator-feedback < Final Year Projects 2016 > SDC-SDF radix-2 pipelined fast Fourier transform architecture, which includes log N – 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve a 100% hardware resource utilization…
A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators Abstract? A one-pin mode transition circuit that addresses the issues related to clock synchronization in switching regulators during the mode transitions between external timing resistor and external clock. The proposed circuit reduces the circuit complexity needed to achieve mode transition during…
A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme Abstract-Previous 6T SRAMs commonly employ a wordline voltage underdrive (WLUD) scheme to suppress half-select (HS) disturbs in read and write cycles, at the expense of reduced cell read current ( I CELL ) and degraded write…
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability Abstract?Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. < final year projects > [numbers_sections number=”1″…
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing Abstract? Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient memory access. In this paper, we propose a configurable parallel architecture to improve the computing efficiency of integral histogram. Based on the…
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply Abstract?A new power-efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation Slides Flow Diagram Database…
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Abstract?Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant sav-ing of computation. However, transpose form configuration does not directly support the block processing unlike direct-form configuration. < final year projects > [numbers_sections number=”1″ title=”Including…
A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic Abstract? A high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in…
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors Abstract? A novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for ef?cient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error < Final Year Projects...
