Showing 193–204 of 206 results
Timing Error Tolerance in Small Core Designs for SoC Applications Abstract? Timing errors are an increasing reliability concern in nanometer technology, high complexity and multi-voltage/frequency integrated circuits. A local error detection and correction technique is presented in this work that is based on a new bit flipping flip-flop. Whenever a timing error is detected, it…
Transactions Briefs Computing Seeds for LFSR-Based Test Generation From Nontest Cubes Abstract?In test data compression methods that are based on the use of a linear-feedback shift register (LFSR), a seed that produces a test for a target fault is computed based on a test cube for the fault. With a given LFSR, a seed may…
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing Abstract? Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. The design and the VLSI implementation of an asynchronous cellular logic array for fast binary image processing. The proposed processor array employs trigger wave propagation and collision detection mechanisms for binary image skeletonization, and…
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM Abstract? Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. A trip-point bit-line precharge TBP sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). < Final Year Project 2016 > This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in…
Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology Abstract? Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a…
Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design Abstract– Very large-scale integrated circuit (VLSI) design, based on today?s CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply voltage, cause new concerns such as high leakage current, and increase in radiation sensitivity….
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product Abstract? The ultralow-voltage (ULV) design strategy for high-speed flash analog-to-digital converters (ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. A new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and…
Unified VLSI architecture for photo core transform used in JPEG XR Abstract? In JPEG XR image compression technique the unified photo core transform is used. It is designed to support high dynamic range and high definition formats thus this type of JPEG XR image compression with unified photo core transform is widely used in real…
Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications Abstract? Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. A stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one…
VLSI Architecture for delay efficient 32-bit Multiplier using Vedic Mathematic sutras Abstract?Abstract This paper presents the VLSI Architecture for High-Speed 32-bit Multiplier using Vedic Mathematic sutras. Two sutras among 16 sutras of Vedic Mathematics can be applied for multiplication. Nikhilam Sutra and Urdhva-Tiryagbhyam Sutra are used to implement Vedic Multipliers. In this paper, VLSI architecture…
VLSI Computational Architectures for the Arithmetic Cosine Transform Abstract? VLSI Computational Architectures for the Arithmetic Cosine Transform. The discrete cosine transform (DCT) is a widely-used and important signal processing tool employed in a plethora of applications. Typical fast algorithms for nearly-exact computation of DCT require ?oating point arithmetic, are multiplier intensive, and accumulate round-off errors….
VLSI Design for SVM-Based Speaker Verification System Abstract? VLSI Design for SVM-Based Speaker Verification System. The chip implementation of a support vector machine (SVM)-based speaker veri?cation system. The proposed chip comprises a speaker feature extraction SFE module, an SVM module, and a decision module. < Final Year Project 2016 >The SFE module performs autocorrelation analysis,…
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