RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing Abstract– An approximate multiplier that is high speed yet energy efficient. The approach is to round the operands to the nearest exponent of two. This way the computational intensive part of the multiplication is omitted improving speed and energy consumption at the…
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures Abstract? Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. Presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip < Final Year Projects 2016 > SoC designs with embedded test data compression. These designs pose significant challenges to the…
Secure Binary Image Steganography Based on Minimizing the Distortion on the Texture Abstract? Most state-of-the-art binary image steganographic techniques only consider the ?ipping distortion according to the human visual system, which will be not secure when they are attacked by steganalyzers. In this paper, a binary image steganographic scheme that aims to minimize the embedding…
Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors Abstract? The increasing number of cores on a chip has made the network on chip (NoC) concept the standard communication paradigm for chip multiprocessors. A fault in an NoC leads to undesirable ramifications that can severely impact the performance of a chip. Therefore, it is vital…
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology Abstract?Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=”…
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology Abstract? Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. Although near-threshold(Vth)operation is an attractive method for energy and performance-constrained applications,it suffers from problems in terms of circuit stability, particularly,for static random…
Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell Abstract? a Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and…
Stochastic Resource Provisioning for Container ized Multi-Tier Web Ser vices in Clouds Abstract-The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are…
Stable, Reliable and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-design Abstract– Space applications demand highly stable and reli-able SRAM circuits for secure and the uninterrupted operation. We propose advanced FinFET and self-refreshing logic based 12T SRAM cell (WWL12T). The dual-k gate insulator and symmetric spacer are used to improve the reliability and…
Stable, Reliable and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-design Abstract– Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted operation. In this paper, we propose advanced FinFET and self-refreshing logic based 12T SRAM cell (WWL12T). The dual-k gate insulator and symmetric spacer are used to improve…
Star-Type Architecture with Low Transmission Latency for a 2D Mesh NOC Abstract? Star-Type Architecture with Low Transmission Latency for a 2D Mesh NOC. The 2D mesh network on chip NOC < Final Year Proejcts 2016 > is a popular NOC topology because of network scalability and the use of a simple routing algorithm. However, the…
Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication Abstract? Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication. Brain-inspired circuits can provide an alternative solution to implement computing architectures taking advantage of fault tolerance and generalization ability of logic gates. In this brief, we advance over the memristive…
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