Performance Analysis and Optimization for Homogenous Multi-core System based on 3D Torus Network on Chip Abstract? 3D IC technology drives Network-On-Chip (NoC) design on towards 3D trend and relevant multi-core system further development. However, most recent researches still focus on the fundamental 3D Mesh structure and have no convincible traffic pattern models in realistic applications….
Pilot Allocation for Distributed-Compressed-Sensing-Based Sparse Channel Estimation in MIMO-OFDM Systems Abstract? the sparse channel estimation problem in multiple-input?multiple-output orthogonal frequencydivision multiplexing (MIMO-OFDM) systems from the perspective of distributed compressed sensing (DCS). It is focused on deterministic pilot allocation of MIMO-OFDM systems to improve the performance of DCS-based channel estimation. By transforming the problem of DCS-based…
POST: Exploiting Dynamic Sociality for Mobile Advertising in Vehicular Networks Abstract?POST: Exploiting Dynamic Sociality for Mobile Advertising in Vehicular Networks. Mobile advertising in vehicular networks is of great interest with which timely information can be fast spread into the network.Given a limited budget for hiring seed vehicles,how to achieve the maximum advertising coverage within a…
Enabling Secure and Efficient Video Delivery through Encrypted In-network Caching Abstract? Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to anew…
Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation Abstract– In the first place, a pre-charged local bit-line sharing (PCLBS) static random access memory (SRAM) for nearthreshold operation is proposed. In previous local bit-line sharing SRAMs, such as average-8T and full-swing local bit-line (FSLB) SRAMs, multiple bit-cells share a local bit-line pair with a small…
Precharge-Free, Low-Power Content-Addressable Memory Abstract?Content-addressable memory (CAM) is the hardware for parallel lookup/search. The parallel search scheme promises a high-speed search operation but at the cost of high power consumption. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation Slides Flow Diagram Database File Screenshots Execution…
Rapidly Tunable Dual-Comb RF Photonic Filter for Ultrabroadband RF Spread Spectrum Applications Abstract?a rapidly frequency-tunable radio frequency (RF) filter using microwave photonics technology for ultrawideband RF spread spectrum applications. A pair of electro-optic frequency combs is arranged as a dispersive tapped delay line in a differential detection configuration to implement a programmable finite impulse response…
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs Abstract?Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized bitline scheme…
Recursive Approach to the Design of a Parallel Self-Timed Adder Abstract?Abstract This brief presents a parallel single-rail self-timed adder.It is based on a recursive formulation for performing multibit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions…
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops Abstract? we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first…
Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches Abstract– Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and…
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block Abstract? Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. A reliable low-power multiplier design by adopting algorithmic noise tolerant ANT architecture with the ?xed-width multiplier to build the reduced precision replica redundancy block (RPR). < Final Year Project 2016 >The proposed ANT architecture can meet…
Free 
