Multiplierless Unity-Gain SDF FFTs Abstract? A novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transforms (FFTs). Previous method s achieve unity-gain FFTs by using either complex multipliers or nonunity-gain rotators with additional scaling compensation. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation Slides…
New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements Abstract?designs of static dual-edgetriggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes…
Vehicle Service Remainder (Android App) Abstract-In this paper, a novel radiation-hardened-by-design (RHBD) 12T memory cell is proposed to tolerate single node upset and multiple-node upset based on upset physical mechanism behind soft errors together with reasonable layout-topology. The verification results obtained confirm that the proposed 12T cell can provide a good radiation robustness. Compared with…
Novel VLSI Architecture for Real Time Medical Image Segmentation Abstract? Novel VLSI Architecture for Real Time Medical Image Segmentation. Image segmentation plays an important role in the processing of medical images. Segmentation of medical images is a challenging task due to the poor image contrast and the diffusion of organs or tissue boundaries. Due to…
On System-on-Chip Testing Using Hybrid Test Vector Compression Abstract? On System-on-Chip Testing Using Hybrid Test Vector Compression. A comprehensive hybrid test vector compression method for very large scale integration (VLSI) circuit testing, targeting specifically embedded coresbased system-on-chips (SoCs). In the proposed approach, a software program is loaded into the on-chip processor memory along with the…
Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter Abstract? An open-loop fractional divider is proposed to eliminate the deterministic jitter caused by the conventional fractional dividers without additional calibration. The proposed divider utilizes a new voltage-comparator-based digital-to-time converter (DTC) as an adjustable delay circuit to control the edges of the output clock of the divider….
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs Abstract? A new effective single-Miller capacitor compensation topology for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage. Moreover, an optimized design strategy which profitably exploits the two left half-plane zeros is…
Optimized Built-In Self-Repair for Multiple Memories Abstract? A new built-in self-repair (BISR) scheme is proposed for multiple embedded memories to find optimum point of the performance of BISR for multiple embedded memories. All memories are concurrently tested by the small dedicated built-in self-test to figure out the faulty memories, the number of faults, and irreparability….
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application Abstract-In the first place, a new design procedure has been proposed for realization of logarithmic function via three phases: 1) differentiation; 2) division; and 3) integration for any arbitrary analog signal. All the basic building blocks, i.e., differentiator, divider, and integrator, are realized by operational…
Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels Abstract? Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels. We present an approach for overcoming computational errors at run time that originate from static hardware faults in digital processors. The approach is based on embedded machine-learning stages that learn and model the statistics…
Partially Parallel Encoder Architecture for Long Polar Codes Abstract? Partially Parallel Encoder Architecture for Long Polar Codes. Due to the channel achieving property, the polar code has become one of the most favorable error-correcting codes. As the polar code achieves the < Final Year Projects 2016 > asymptotically, however, it should be long enough to…
Partially Repeated SC-LDPC Codes for Multiple-Access Channel Abstract?A simple partially repeated spatially coupled low-density parity-check (SC-LDPC) code is proposed for a multiple-access channel (MAC) with a large number of users. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation Slides Flow Diagram Database File Screenshots Execution…
Free 
