Showing 145–156 of 206 results
Low-Power Programmable PRPG With Test Compression Capabilities Abstract? Low-Power Programmable PRPG With Test Compression Capabilities. A low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test BIST < Final Year Project 2016 > based pseudorandom test pattern generators. It is…
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Abstract?Abstract In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type…
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units Abstract?Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation…
Low-power technique for dynamic comparators Abstract?Comparators are the key building blocks of the ADCs. The speed and the power consumption of the comparators play an important role in the characteristics of today ? s commonly used ADCs < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation…
LLow?power half?select free single?ended 10 transistor SRAM cell Abstract?Abstract This paper proposes a novel sub threshold 10T SRAM cell. The proposed design removes the half-select issue which is a problem in SRAM array as observed in the case of conventional 6T and 8T cells. Since the proposed cell is free from half-select disturb, bit-interleaving scheme…
LUT Optimization Distributed Arithmetic – based BLMS Abstract? We analyze the contents of lookup tables (LUTs) of distributed arithmetic (DA)-based block least mean square (BLMS) adaptive filter (ADF) and based on that we propose intra-iteration LUT sharing to reduce its hardware resources, energy consumption, and iteration period. The proposed LUT optimization scheme offers a saving…
MACS: A Highly Customizable Low-Latency Communication Architecture Abstract?Networks-on-chips (NoCs) are an increasingly popular communication infrastructure in single chip VLSI design for enhancing parallelism and system scalability. Processing elements (PEs) connect to a communication topology via NoC switches, which are responsible for runtime establishment and management of inter-PE communication channels. < final year projects > [numbers_sections…
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores Abstract? : The increased use of multicore chips diminishes per-core complexity and also demands parallel design and test technologies. An especially important evolution of the multicore chip has been the use of multiple identical cores, providing a homogenous system with various merits. Introduces a…
Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression Abstract?A new compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed scheme stores only the range of state metrics as well as two indexes of the maximum and minimum values. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no”…
Modeling and Design of EMI-Immune OpAmps in 0.18-? m CMOS Technology Abstract? The modeling and design of Miller-based operational amplifier structures that are highly im-mune to electromagnetic interference (EMI). The proposed CMOS Miller-based operational amplifier is derived using the present modeling. It provides higher immunity to EMI that is injected into the amplifier?s input over…
Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells Abstract– In energy-constrained applications, SRAM systems operating in the subthreshold region are often deployed to reduce power consumption. Subthreshold SRAM designs, however, confront numerous challenges, such as susceptibility to process variation and reduced ON?OFF current ratio. Statistical modeling of the variation in cell…
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM Abstract? Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest because of its characteristics of nonvolatility (i.e., zero standby power) and small cell size (i.e., high density and high performance). As the technology node is scaled down, however, the sensing margin of…
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