Showing 133–144 of 206 results
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers Abstract? An on-line transparent test technique for detection of latent hard faults which develop in first input first-output buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test…
Information Hiding as a Challenge for Malware Detection Abstract?Information Hiding as a Challenge for Malware Detection. We?re experiencing an exponential growth in mali- cious software. According to the antivirus research firm AV- TEST, 2014 saw approximately 130 million new forms of malware, compared to just over 80 million in 2013 and about 30 million in…
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding Abstract?The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation…
Intelligent FPGA Data Acquisition Framework Abstract– In the first place, present the FPGA-based framework IFDAQ which is used for the development of data acquisition systems for detectors in high energy physics. The framework supports Xilinx FPGA and provides a collection of IP cores written in VHDL which use the common interconnect interface. The IP core…
Low Power Address Generator for Memory Built-In Self Test Abstract-Memory is one of the basic computer components that is intensively accessed. Therefore, it is more likely to be affected by manufacturing faults rather than other components in the System on Chip (SoC). Memory Built-in Self Test (MBIST) is the most commonly used to test embedded…
Low power Memristor Based 7T SRAM Using MTCMOS Technique Abstract? Low power Memristor Based 7T SRAM Using MTCMOS Technique. In recent years demand of low power devices is increasing and the reason behind this is scaling of CMOS technology. Due to the scaling, size of the chip decreases and number of transistor in system on…
Low-Computing-Load, High-Parallelism Detection Method based on Chebyshev Iteration for Massive MIMO Systems with VLSI Architecture Abstract-Minimum-mean-square-error (MMSE) detection is becoming increasingly relevant in signal detection for massive multiple-input-multiple-output (MIMO) systems because of the increasing numbers of both users and antennas. This paper proposes a signal detection method called parallelizable Chebyshev iteration (PCI) that reduces the…
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Abstract?This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at…
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Abstract? Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication. a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA)…
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates Abstract-In this paper, novel circuits for XOR/XNOR and simultaneous XOR?XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six…
Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop Abstract?Abstract We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To…
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia Abstract? The design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract…
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