Hard-Information Bit-Reliability Based Decoding Algorithm for Majority-Logic Decodable Nonbinary LDPC Codes Abstract?A modified bit-reliability based decoding algorithm is presented based on a recent work by Huang et al .For the presented algorithm, only one Galois field element is passed and exchanged along the edges of the Tanner graph. < final year projects > [numbers_sections number=”1″…
Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers Abstract?a hardware and energy-efficient stochastic lower?upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the complex arithmetic operations in LUD can be performed with simple logic gates. With proposed dual partition computation method, the stochastic multiplier and divider exhibit high computation accuracy…
High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels Abstract?In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve…
?High throughput Pipelined 2d Discrete Cosine Transform? for Video Compression Abstract?AbstractRecent development of digital video compression technology, high quality video applications like HDTV are popular. Within the close to future, next-generation video devices can have a lot of higher definition and determination like UHD (Ultra High Definition) TV. In these services, multimedia system information increase…
High- Throughput Area – Efficient Processor for Cryptography Abstract-Cryptography circuits for portable electronic devices provide user authentication and secure data communication. These circuits should, achieve high performance, occupy small chip area , and handle several cryptographic algorithms. This paper proposes a high performance ASIP ( Application specific instruction set processor ) for five standard cryptographic…
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2 m ) Abstract? An efficient pipelined architecture of elliptic curve scalar multiplication (ECSM) over GF(2M ). The architecture uses a bit-parallel finite-field (FF) multiplier accumulator (MAC) based on the Karatsuba?Ofman algorithm. The Montgomery ladder algorithm is modified for better sharing of execution paths. The data…
High-Sensitivity CMOS RF-DC Converter in HF RFID Band Abstract? A fully-integrated RF-DC converter operating at the HF RFID working frequency (13.56 MHz) and realized in 350 nm CMOS technology is presented. It is based on a Dickson?s rectifier, a Pelliconi?s charge pump driven by a 50 kHz ring oscillator, and a voltage monitor. Mathematical model…
High-Speed,Low-Power,and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator Abstract?A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete…
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule Abstract? High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. Architecture of block-level-parallel layered decoder for irregular LDPC code. It can be recon?gured to support various block lengths and code rates of IEEE 802.11n Wi Fi wireless-communication standard.< Final Year...
Hybrid LUT/Multiplexer FPGA Logic Architectures Abstract?Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. < final year projects > [numbers_sections number=”1″ title=”Including =Packages=” last=”no” ] Complete Source Code Complete Documentation Complete Presentation Slides…
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application Abstract? Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. Behavior of adiabatic logic circuits in weak inversion or sub threshold regime is analyzed in depth for the ?rst time in the literature to make great improvement in ultra-low power circuit design. This novel approach is ef?cacious in…
Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures Abstract? Coarse-grained reconfigurable architecture (CGRA) is a promising architecture with high performance, high power efficiency, and attraction of flexibility. The computation-intensive portions of applications, i.e., loops, are often implemented on CGRAs for acceleration. The loop pipelining techniques are usually used to exploit the parallelism of loops. However,…
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