0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier Abstract? A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. < final...
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage Abstract– We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged…
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-BandQuasi-ANSIS1.111/3 Octave Digital Filterbank for Hearing Aids Abstract?11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids. A novel algorithm and architecture design for 18-band quasi-class-2 ANSI S1.11 1/3 octave ?lter bank. The proposed design has several advantages such as lower group delay,…
28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression Abstract-With the development of modern semiconductor fabrication technology, the channel length of the CMOS device and the device pitch continually shrink accompanied by more and more severe process variation and signal coupling effect, respectively. In this paper, we explain how the coupling effect interferes with the action…
75 GBd InP-HBT MUX-DAC module for high-symbol-rate optical transmission Abstract? Owing to the spread of broadband applications, data traffic in optical communication networks is continuously increasing. High-symbol-rate optical transmission schemes with advanced multi-level modulation formats, such as M-ary quadrature amplitude modulation (QAM), are now being investigated as to their suitability for future cost-effective 1 Tb/s-class…
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 ? m CMOS Technology for Implantable Medical Applications Abstract? A 0.45-V low-power 0.18 ?m CMOS OOK/FSK RF receiver for implantable medical applications is proposed. The re-ceiver utilizes a wake-up mechanism to adjust its power consumption automatically by reading the amplitude of the input wireless OOK/FSK modulated RF…
A 0.45-V, 14.6-nW CMOS Subthreshold Voltage Reference With No Resistors and No BJTs Abstract?A low-voltage low-power CMOS sub-threshold voltage reference with no resistors and no bipolar junction transistors in a wide temperature range. The temperature stability is improved by second-order compensation. By employing a bulk-driven technique and the< Final Year Projcts 2016 > MOS transistors…
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process Abstract?a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a…
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme Abstract? A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme. A 3.5 GS/s 6-bit current-steering digital-to-analog converter DAC with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC…
A 32 kb 0.35?1.2 V, 50 MHz?2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS Abstract-An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35?1.2 V at all process corners. A differential read asymmetric…
A 40?170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS Abstract? A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplifier (PA) is described. A PLL-based architecture is employed, which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which…
A 6 b 5 GS/s 4 Interleave d 3 b/Cycle SAR ADC Abstract?This paper presents a 4? time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b /cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls…
